1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device with an recessed gate structure, and more particularly to a method of manufacturing a static induction transistor (hereinafter referred to as "SIT") or a vertical field-effect transistor (hereinafter referred to as "Vertical FET").
2. Description of the Prior Art
A conventional gate structure of SIT includes a planar type wherein a gate region 3 is formed into the same plane as that of a surface main electrode 4 (source or drain) as shown in FIG. 3, and a buried gate type wherein a gate portion 13 is completely embedded into a high resistance epitaxial layer (channel region) 12 as shown in FIG. 4. The gate structure shown in FIG. 3 comprises a semiconductor substrate 1, a high resistivity epitaxial layer (channel region) 2, a gate Al electrode 5, a source (or drain) Al electode 6, and an insulating layer 7. In FIG. 4, reference numeral 11 denotes a semiconductor substrate (drain or source), 14 a surface main electrode (source or drain), 15 a gate Al electrode, 16 a source (or drain) Al electrode, 17 a buried gate connection portion and 18 an insulating layer.
The planar type SIT shown in FIG. 3 can be optimized and integrated similar to other planar type devices (such as bipolar, MOS etc.) and is applied to logic IC etc. which utilize high speeds thereof. However, a distance between the gate region 3 and the surface main electrode 4 secured is small in terms of structure and they are nearly overlapped. The junction of this kind has a high breakdown susceptibility and also the junction leak current is relatively high, thus posing a problem in terms of operating margin of the circuit, reliability, power consumption and the like.
On the other hand, in case of the buried type SIT shown in FIG. 4, it is necessary to have a distance large enough to prevent the buried gate portions 13 from being joined during the epitaxial growth, which makes optimization and integration difficult. Thus, this type of SIT is used as a discrete device such as a power transistor. A further disadvantage is that since the capacitance between the gate portion 13 and the surface main electrode 14 is large, it is difficult to operate at a high speed.
In order to overcome the drawbacks encountered in the aforesaid planar and buried gate type SITs, an recessed gate SIT as shown in FIG. 5 has been proposed. In this proposal, a high resistivity epitaxial layer (channel region) 32 is formed on a semiconductor substrate 31 serving as a drain or source, and thereafter recess-etching is applied thereto followed by addition of an impurity to the bottom to form a gate region 33. A surface main electrode (source or drain) region 34 is formed on the surface of the epitaxial layer 32 between the gates, and thereafter the surface is coated with an insulating layer 35. A gate Al electrode 36 and a source (or drain) electrode 37 connected to the gate region 33 and the surface main electrode region 34, respectively; are formed. According to the aforesaid recessed gate SIT, sufficient distance can be provided between the gate region 33 and the surface main electrode 34 of the structure, and therefore, the break-down susceptibility in this junction is low and also the junction leak current may be restricted to be low. In addition, since to some extent there is a freedom in positioning of the gate region 33 with respect to the channel region 32 between the main electrodes 31 and 34, this recessed gate SIT can be advantageously designed to have a larger voltage amplification constant, .mu. than that of the planar type.
However, in case of this recessed gate structure, it is difficult to form a gate electrode on the lower portion recessed by several .mu.m after etching. That is, it is naturally difficult to coat a photosensitive resin photoresist (normally, approximately l.mu.m of thickness) on the convex-concave surface uniformly. Very cumbersome means has to be used to overcome such difficultites, failing to realize putting it to practical use for these reasons.